The present invention relates to a data packet switching node to be used in an asynchronous digital network.
A frame switching relay is described in U.S. Pat. No. 5,237,564. According to this patent, such a frame switching relay comprises n input ports and n output ports each of them having an identical binary bit rate D. The switching relay comprises a time base at a frequency that is integral multiple of the binary rate D. From this time base and by means of frequency dividers, numerous clock signals required for the various functions of the frame switching relay are derived. As a consequence, the internal implementation of the frame switching relay is determined by the bit rate D of the input and output ports.
However, the implementation of a switching fabric with ports supporting very high bit rates (i.e., 9.6 Gbps and above) is at the limit of technological feasibility and as a consequence very expensive. Indeed, even if a packet switching relay has only to accommodate one port at 9.6 Gbps, all other ports being used at lower bit rates, the frame switching relay must be designed as if all ports were to accommodate a bit rate of 9.6 Gbps. A further disadvantage is that the resource of the switching fabric are wasted if the whole switching fabric is designed for very high bit rates while several ports accommodate lower bit rates.